A. Field of the Invention
This invention relates to data communication bus structures, and particularly to an improved method of controlling a data communications bus which provides improved fault tolerance provisions.
B. Description of the Prior Art
The following prior art provides useful background information for the present invention:
(1) An article entitled "A Systematic Approach to the Design of Digital Busing Structures", by K. Thurber and E. Jensen, published in the 1972 Proceedings of the Fall Joint Computer Conference beginning at page 719. PA0 (2) IBM Technical Disclosure Bulletin, Volume 12, Number 1, June 1969, page 163, entitled "Line Adapter Configuration for Fault Location". PA0 (3) IBM Technical Disclosure Bulletin, Volume 9, Number 5, October 1966, page 454, entitled "Automatic Channel Switching". PA0 (4) IBM Technical Disclosure Bulletin, Volume 8, Number 3, August 1965, page 393, entitled "Real Time Checking of Selector Channel Sequence Controls by Time Shared Central Processor Sequence Controls". PA0 (5) U.S. Pat. No. 3,351,905 for "Error Checking Method and Apparatus", granted to D. Kramer on Nov. 7, 1967. PA0 (6) U.S. Pat. No. 3,434,115 for "Timed Operation Sequence Controller", granted to J. S. Chomicki on March 18, 1969. PA0 (7) U.S. Pat. No. 3,517,171 for "Self-Testing and Repairing Computer", granted to A. A. Avizienis on June 23, 1970. PA0 (8) U.S. Pat. No. 3,534,337 for "Data Acquisition Device", granted to H. Martin et al on Oct. 13, 1970. PA0 (9) U.S. Pat. No. 3,536,902 for "Sequence Step Check Circuit", granted to A. S. Cochran et al on Oct. 27, 1970. PA0 (10) U.S. Pat. No. 3,646,519 for "Method and Apparatus for Testing Logic Functions in a Multiline Data Communication System", granted to J. E. Wollum et al on Feb. 29, 1972. PA0 (11) U.S. Pat. No. 3,648,256 for "Communications Link for Computers", granted to T. O. Paine et al on Mar. 7, 1972.
Reference (1) is a general discussion of digital busing structures, and does not contemplate a structure according to the present invention, particularly the use of four control sub-buses, two for control information and two for control timing. It also does not discuss any fault tolerant considerations.
Reference (2) deals with a communication line rather than a general digital bus structure. It does not check signaling on line and is not programmable, as is the present invention.
Reference (3) does not provide time-sensitive signaling as used in the present invention.
Reference (4) does not contemplate the use of separate sub-buses to provide control information and control signals.
Reference (5) is directed to an error checking method and apparatus which does not employ plural sub-buses, checking of bus signal timing or programmable interfaces, as found in the present invention.
Reference (6) is directed to a "timed operation sequence controller" and neither shows nor describes any interface unit or bus structure as disclosed and claimed herein.
Reference (7) shows a data processing system using bus monitors, but the monitors are merely error detectors for the error detecting data codes used in the system. No character validation or protocol timing check is provided, as it is in the present invention.
Reference (8) is directed to a data acquisition circuit, using common channels between a plurality of field locations and a central location, and does not contemplate sub-buses for both control information and control signals. Nor does it provide a unique monitoring system or an interface unit of the programmable type, as found in the present invention.
Reference (9) is directed to a sequence step checking circuit for a telephone switching system and is unrelated to data bus structures.
Reference (10) is directed to a system for checking operation of digital logic on command from a processor, whereas the present invention is directed to a continually operating checking system of all time signaling over a bus. Also, this reference does not disclose the use of a programmable interface unit.
Reference (11) is directed to a serial bus structure with some failure detection and retry procedures, whereas the present invention relates to general parallel bus structures having both control and data signals.
The prior art discussed above represents what applicant and his representatives personally and presently consider to be the best of the prior art presently known to them. No representation is made or intended, however, that better prior art does not exist, nor is any representation made or intended that the foregoing interpretations are the only interpretations that can be placed on this prior art.